In recent years, an LSI circuit having a large number of data transfer ports corresponding to a high-speed data transfer standard is used in server apparatuses, network apparatuses, and so forth. Examples of the high-speed data transfer standard include 10-GIGABIT ETHERNET (IEEE802.3ae standard) and PCI (Peripheral Component Interconnect)-Express.
For an LSI circuit intended for high-speed data transfer, higher speed and higher performance are sought after and, in addition, reductions in cost and power consumption are demanded. For this purpose, a data transmitting/receiving circuit is densified such that one LSI circuit includes a plurality of data transfer ports (channels).
In general, a data transmitting circuit includes a driver circuit, a PLL (Phase Locked Loop) circuit that generates a clock, and so forth. The PLL circuit occupies a large proportion of the circuit area in an LSI circuit, and also consumes high power compared to other circuits. Thus, if a PLL circuit is provided for each channel in the case where a plurality of data transfer ports are provided in one LSI circuit, the PLL circuits occupy a larger proportion of the entire area in the LSI circuit, and also consume higher power. Therefore, in a data transmitting circuit, it is common for driver circuits for a plurality of channels to share one PLL circuit.
There is proposed a deserializer circuit network for a high-speed serial data receiver on a programmable logic device integrated circuit that converts serial data into parallel data with a desired data width.
However, a conventional circuit does not transmit at a different data rate independently selected for each channel using one high-speed clock.